Multicast support in multi-chip centralized schedulers in Input Queued switches |
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Authors: | Andrea Bianco Alessandra Scicchitano |
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Affiliation: | 1. Dipartimento di Elettronica, Politecnico di Torino, Corso Duca, degli Abruzzi 24, 10129 Torino, Italy;2. IBM Research, Zurich Research Laboratory, 8803 Ruschlikon, Switzerland;1. Petersburg Nuclear Physics Institute, Russia;2. NRC “Kurchatov Institute”, Russia;3. CERN, Switzerland |
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Abstract: | IQ switches store packets at input ports to avoid the memory speedup required by OQ switches. However, packet schedulers are needed to determine an I/O (input/output) interconnection pattern that avoids conflicts among packets at output ports. Today, centralized, single-chip, scheduler implementation are largely dominant. In the near future, the multi-chip scheduler implementation will be needed to reduce the hardware scheduler complexity in very large, high-speed, switches. However, the multi-chip implementation implies introducing a non-negligible delay among input and output selectors used to determine the I/O interconnection pattern at each time slot. This delay, mainly due to inter-chip latency, requires modifications to traditional scheduling algorithms, which normally rely on the hypothesis that information exchange among selectors can be performed with negligible delay. We propose a novel multicast scheduler, named IMRR, an extension of a previously proposed multicast scheduling algorithm named mRRM, making it suitable to a multi-chip implementation, and examine its performance by simulation. |
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