Fast and scalable lock methods for video coding on many-core architecture |
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| Affiliation: | 1. Institute of Information Engineering, Chinese Academy of Sciences, National Engineering Laboratory for Information Security Technologies, Beijing, China;2. Institute of Microelectronics, Tsinghua University, Beijing, China;3. Key Lab. of Intelligent Information Processing, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China;4. School of Information Science and Engineering, Shandong Normal University, Jinan, China;5. Department of Computer Science and Technology, Beijing University of Chemical Technology, Beijing, China;6. State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China;1. Sichuan Province Key Lab of Signal and Information Processing, Southwest Jiaotong University, Chengdu 610031, PR China;2. School of Computer & Information Engineering, Yibin University, Yibin 644000, PR China;1. L.I.M. Faculty of Sciences Dhar el Mahraz, USMBA, FÃs¨, Morocco;2. DESTEC, FLSHR, University of Mohammed V-Agdal, Rabat, Morocco;3. Institut Polytechnique Bordeaux/ENSEIRB-MATMECA, Laboratoire IMS CNRS UMR 5218, Groupe Signal et Image, France;4. LRIT URAC 29, University of Mohammed V-Agdal, Rabat, Morocco;1. Key Lab of Intelligent Computing and Signal Processing of Ministry of Education, School of Computer Science and Technology, Anhui University, Hefei, Anhui, China;2. Department of Computer Science and Engineering, University of Texas at Arlington, Engineering Research Building, Room 529, 500 UTA Blvd, Arlington, TX 76019, USA;1. Computer and Information Technology Department, Zhejiang Police College, China;2. College of Computer Science, Zhejiang University, China |
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| Abstract: | Many-core processors are good candidates for speeding up video coding because the parallelism of these applications can be exploited more efficiently by the many-core architecture. Lock methods are important for many-core architecture to ensure correct execution of the program and communication between threads on chip. The efficiency of lock method is critical to overall performance of chipped many-core processor. In this paper, we propose two types of hardware locks for on-chip many-core architecture, a centralized lock and a distributed lock. First, we design the architectures of centralized lock and distributed lock to implement the two hardware lock methods. Then, we evaluate the performance of the two hardware locks and a software lock by quantitative evaluation micro-benchmarks on a many-core processor simulator Godson-T. The experimental results show that the locks with dedicated hardware support have higher performance than the software lock, and the distributed hardware lock is more scalable than the centralized hardware lock. |
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| Keywords: | Many-core Hardware lock Centralized lock Distributed lock Micro-benchmarks Godson-T Software lock Single-core processor |
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