| 集成电路封装陶瓷外壳埋线电阻的设计 |
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| 引用本文： | 余咏梅. 集成电路封装陶瓷外壳埋线电阻的设计[J]. 微电子技术, 2001, 29(6): 24-26 |
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| 作者姓名： | 余咏梅 |
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| 作者单位： | 福建南平闽航电子器件公司, |
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| 摘 要： | 本文介绍了集成电路封装外壳埋线电阻的设计方法以及在工艺上如何应用浆料配比、间隙填充、通孔穿层等途径来降低外壳埋线电阻值。
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| 关 键 词： | 集成电路 封装外壳 埋线电阻 陶瓷 电路设计 |
| 文章编号： | 1008-0147(2001)06-24-03 |
| 修稿时间： | 2001-09-18 |
Design of Buried Resistor of Ceramic Package for IC |
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| YU Yong-mei. Design of Buried Resistor of Ceramic Package for IC[J]. Microelectronic Technology, 2001, 29(6): 24-26 |
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| Authors: | YU Yong-mei |
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| Abstract: | The design of buried resistor of ceramic package used for IC is introduced in the paper.The processing such as how to determine the ratio of metal slurry,to fill gap properly and via through multi-layers,are also mentioned,the purpose is to reduce the value of buried resistance. |
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| Keywords: | Package of IC Buried resistor Metal slurry Interconnecting via through Gapfilling |
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