| 5. 8GHz 堆叠式功率放大器设计 |
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| 引用本文： | 陈 涛,田 婷,吴建辉,高 怀.5. 8GHz 堆叠式功率放大器设计[J].微波学报,2014,30(3):77-79. |
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| 作者姓名： | 陈 涛 田 婷 吴建辉 高 怀 |
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| 作者单位： | 1. 东南大学国家ASIC 系统工程技术研究中心; 2. 射频功率器件及电路工程技术研究中心 |
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| 摘 要： | 基于2mm GaAs HBT 工艺,采用堆叠晶体管结构设计了一款5. 8GHz 功率放大器。通常堆叠式功率
放大器在高频情况下,上下两层晶体管间需要电感来完成功率匹配,在芯片设计中其电感会增加版图面积和级间功
耗,为此该设计则利用上层晶体管的基极与地之间的串联电阻、电容等效成堆叠结构级间的感性负载,从而减小了
级间的损耗与匹配难度。实测结果表明,该堆叠功率放大器在5. 8GHz 时增益为20. 6dB,饱和输出功率为29dBm,饱
和输出时功率附加效率达到36. 4%,芯片面积仅为1×0. 85mm2
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| 关 键 词： | 功率放大器 堆叠晶体管结构 级间匹配 |
Design of a 5. 8GHz Stacked Power Amplifier |
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| CHEN Tao,TIAN Ting,WU Jianhui,GAO Huai.Design of a 5. 8GHz Stacked Power Amplifier[J].Journal of Microwaves,2014,30(3):77-79. |
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| Authors: | CHEN Tao TIAN Ting WU Jianhui GAO Huai |
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| Affiliation: | 1. National ASIC System Engineering Research Center, Southeast University; 2. RF Power Device and Circuit Engineering Research Center |
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| Abstract: | A 5. 8GHz power amplifier (PA) using 2mm GaAs HBT is developed. The proposed PA is designed based
on a stacked circuit topology. At high frequency, the optimum impedance of the bottom transistors is not purely resistive, but
has some inductive. This interstage inductor would increase the layout area and bring some ohmic loss. In this design, this
optimum impedance is achieved by adjusting the series resistance and capacitance between the base of the upper transistors
and the ground. The measurement results of the PA exhibits the small signal gain higher than 20. 6dB, and the saturation
output power higher than 29dBm with a power added efficiency of 36. 4% at 5. 8GHz. The chip size is 1×0. 85 mm2 . |
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| Keywords: | power amplifier stacked HBT structure inter-stage matching |
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