基于Astro的时钟树综合

时钟树综合是芯片后端设计至关重要的一环，时钟偏差成为限制系统时钟频率的主要因素。本文以一款TSMC0．25μm工艺的RISC微处理器芯片为例．介绍了使用Synopsys公司的P8LR工具Astro进行时钟树综合和优化的方法，并与Silicon Ensemble在综合后的时钟偏差上作了对比，结果显示使用前者比后者时钟偏差减小百分之十四以上。

Methodology of Clock Tree Synthesis Based on Astro

Clock Tree Synthesis is important in the backend-end design of chip design,and the clock skew has become the major part of constraints that limit system clock frequency. A methodology is explored to do Clock Tree Synthesis and Optimization using Astro tool of Synopsys by experimentation on a RISC MCU chip which is implemented in TSMC 0.25 micron process.We also compare Astro with Silicon Ensemble on clock skews after Clock Tree Synthesis.Our experimental results indicate the skew using Astro synthesis is smaller than using Silicon Ensemble.