GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSI's |
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| Authors: | Higashisaka N Shimada M Ohta A Hosogi K Tobita Y Mitsui Y |
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| Affiliation: | Optoelectron. & Microwave Devices Lab., Mitsubishi Electr. Corp., Hyogo; |
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| Abstract: | GaAs 2.5 Gbps 16 bit MUX/DEMUX LSI's have been successfully developed. DCFL is employed as a basic gate in order to reduce the power dissipation. To avoid the speed degradation caused by using DCFL, various technologies such as 8×2(MUX)/2×8(DEMUX) data conversion processes, a Selector Merged Shift Register, clock overlapping, and a 0.7-μm BPLDD MESFET, have been introduced. Moreover the ECL I/O level interface and single power supply features make it easy to use MUX/DEMUX in optical communication systems. The maximum operating data rate is 3.2 Gbps for both LSI's, and the power dissipation of chips which operates with 2.5 Gbps are as low as 1.3 W for each MUX/DEMUX |
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