CMOS logic cell switching speed thermal characterisation |
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Authors: | Shoucair F.S. |
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Affiliation: | Yale University, Department of Electrical Engineering, New Haven, USA; |
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Abstract: | A study of the switching speed performance of basic CMOS logic cells in the (junction) temperature range 25?250°C is reported. Experimental measurements for capacitively loaded inverters and NAND gates of two standard 4 ?m CMOS processes are compared to theory and to SPICE2G. 6 simulations. It is found that, to a good approximation, a simple delineation factor (lying between 0.004 and 0.006/deg C in this study), applied to the average gate delay at a given temperature, correctly predicts this parameter. Logic cells are thereby typically found to be up to 65% slower at 250°C than they are at room temperature. |
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