一种可重构的快速有限域乘法结构

在一种改进的串行乘法器的基础上，提出了一种可重构的快速有限域GF (2m )(1＜mM)乘法器结构。利用一组配置信号和逻辑电路来改变有限域的度m，使得乘法器可以重构和编程。同时采用门控时钟减小电路功耗。该乘法器结构具有可重构性、高灵活性和低电路复杂性等特点。与传统的移位乘法器相比，它将乘法器速度提高一倍。这种乘法器适合于变有限域，低硬件复杂度的高性能加密算法的VLSI设计。

Reconfigurable and Fast Finite Field Multiplier Architecture

A reconfigurable and fast architecture over Galois field GF (2m )(1＜mM) is presented based on the improved serial multiplier. The value m, of the irreducible polynomial degree, can changed by adding a set of configuring signals and logic circuits, which results in that the multiplier architecture is reconfigurable and programmable without changing the hardware. The proposed multiplier architecture has high order of flexibility and low hardware complexity. Compared with the traditional serial multiplier, it can obtain twice speed-up. It suits high-security cryptographic applications with variable finite fields and low complexity requirements.