Reliable ultra-low-voltage low-power probabilistic-based noise-tolerant latch design

In this paper, we proposed a reliable ultra-low-voltage low-power latch design based on the probabilistic-based Markov random field (MRF) theory ,  and  to greatly improve the ability of noise-tolerance. Through MRF mapping decomposition, we map the previous state and the current state compatible logic function of the latch into the MRF network separately. In this way, we can overcome the challenge of applying Markov random field theory to sequential noise-tolerant circuits. In order to further lower the hardware cost and circuit complexity of the chip, we apply the absorption law and H-tree logic combination techniques 4] to simplify the circuit complexity of the MRF noise-tolerant latch circuit. To preserve the noise tolerant capability of MRF latch, we utilize the cross-coupled latching mechanism in the output of MRF latch. Finally, we apply the proposed MRF latch design in a 16-bit carry-lookahead adder circuit. In TSMC 90 nm CMOS process, our proposed circuit can operate reliably under a lower supply voltage of 0.55 V with superior noise tolerance and consumes only 31 μW power, which is 59.2% lower as compared with the conventional CMOS latch design.