| 时序功能块的提取 |
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| 引用本文： | 潘日华,童家榕,唐璞山. 时序功能块的提取[J]. 计算机辅助设计与图形学学报, 1999, 11(1): 89-92 |
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| 作者姓名： | 潘日华 童家榕 唐璞山 |
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| 作者单位： | 复旦大学电子工程系IC CAD实验室,上海,200433 |
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| 摘 要： | 介绍了基于功能块提取器（ＤＬＦＥ）工具的时序功能块提取工具和方法。整套工具用于从版图中构造层次化电路，以利于电路的验证和理解。时序功能块提取通过时序功能块的普遍特征来定位时序功能块，避免了手工定位的盲目性，大大加快了构造层次化电路的速度。实验证明，工具对时序模块的提取是十分有效的。
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| 关 键 词： | 功能块提取 时序功能块 逻辑验证 |
EXTRACTION OF SEQUENTIAL FUNCTIONAL BLOCK |
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| PAN Ri-Hua,TONG Jia-Rong,TANG Pu-Shan. EXTRACTION OF SEQUENTIAL FUNCTIONAL BLOCK[J]. Journal of Computer-Aided Design & Computer Graphics, 1999, 11(1): 89-92 |
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| Authors: | PAN Ri-Hua TONG Jia-Rong TANG Pu-Shan |
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| Abstract: | To construct hierarchical circuit from layout, properties of sequential module are utilized to extract sequential modules out of netlist. The work is based on DLFE (Digital Logic Functional block Extractor). With the tool's help, objectless manual searches of sequential module during the use of DLFE are avoided and construction of hierarchical circuit are greatly speeded. |
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| Keywords: | functional block extraction sequential module logic verification |
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