基于FPGA的一种存储器字节访问方法

计算机系统普遍采用较宽的存储器总线结构以提高吞吐率，这导致了以字节为基本单位读写数据的不便。通过对主流SDRAM存储器的访问机制的分析，为SDRAM存储控制器设计了一种数据自动对齐方案，该方案能够根据输入的字节地址和数据自动产生所需的存储器控制信号，并将数据对齐到正确的字节位置。详细阐述了生成地址、字节控制信号以及进行字节对齐的原理与方法，并在FPGA芯片上实现。与基于Cache以及基于两次存储器读写操作的方案相比较，新方案占用硬件资源更少，存储器带宽利用率更高。

Byte access method for wide data bus memory based on FPGA

It is a widely accepted approach to use wide data bus to increase the data accessing speed. However, this method causes the inconvenience on reading and writing data in bytes. The common operation mechanism of current mainstream SDRAM memory chip was analyzed, and a new byte alignment method was proposed for the SDRAM controller. Based on the given byte-address and input data, the new method could generate correct address and byte control signals, also aligned the bytes to the corresponding positions. The architecture and processing flow were illustrated in detail, as well as the implementation on Field Programmable Gate Array (FPGA) chips. Compared with other schemes based on memory cache and twice-memory-access, this method costs fewer hardware resources and memory bandwidth.