Determination of bulk trap parameters using thermal dielectric relaxation techniques

A new non-steady-state technique for determining the energy levels of traps through which electron-hole pairs are generated in the depletion-layer of the silicon of metal-oxide-silicon (MOS) capacitor structures has been applied to metal-nitride-oxide-silicon (MNOS) structures. The technique consists of cooling the device to low temperatures and biasing it into the deep-depletion mode. The temperature of the device is then raised at a constant rate and the resulting I_g-T characteristic exhibits a pronounced wide peak. The energy level of the traps involved in the generation process was obtained from the slope of the log_eI_g - 1/T plot of the leading edge of the I_g-T characteristic curve, and is found to be 0·55 eV.A cross-check on the trap levels involved in the generation process was made by performing the experiment at two heating rates, β₁ and β₂. From a knowledge of the corresponding temperatures at which the maxima of the two peaks in the I_g-T characteristics occur, the energy level of the traps was found to be 0·54 eV. Furthermore, having obtained the trap level, the so-called carrier lifetime, τ, was found to be approximately 4μ sec.Experiments are described which provide convincing evidence that the generation of electron-hole pairs occurs in the depletion-layer of the silicon rather than at the silicon-silicon interface.