Measurement of transient effects in SOI DRAM/SRAM accesstransistors

Bitline-induced transient effects in access transistors pose a problem in SOI DRAM and SRAM cells. The floating-body potential is affected by the bitline so changes in the bitline potential may upset the charge stored in the memory cell. Transient effects in SOI access transistors are measured versus the time the bitline is at high voltage, and V_DD for fully- and partially-depleted SOI devices. Bulk devices show no bitline-induced transient effects. Measurements show that the magnitude of the charge upset can be large enough to disturb the charge stored in DRAM and SRAM cells. Measurements also show that for any substantial upsets to occur, the time the bitline has to be at high voltage is on the order of milliseconds. Although the effect of bitline transitions is cumulative, the amount of charge upset when the bitline switches rapidly (i.e., millisecond periods) is shown to be negligible. Thus, proper design of SRAM upset-charge protection and DRAM refresh time should circumvent this problem