The designs of a scalable optical packet switching architecture |
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| Authors: | Wang‐Rong Chang Ho‐Ting Wu Kai‐Wei Ke Hui‐Tang Lin |
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| Affiliation: | 1. Department of Electrical Engineering , National Cheng Kung University , No. 1, Ta‐Hsueh Road, Tainan 701, Taiwan;2. Department of Computer Science and Information Engineering , National Taipei University of Technology , No. 1, Sec. 3, Chung‐Hsiao E. Rd., Taipei 106, Taiwan Phone: 886–2–27712171 ext. 4221 Fax: 886–2–27712171 ext. 4221 E-mail: htwu@csie.ntut.edu.tw.;3. Department of Computer Science and Information Engineering , National Taipei University of Technology , No. 1, Sec. 3, Chung‐Hsiao E. Rd., Taipei 106, Taiwan;4. Institute of Computer and Communication Engineering , National Cheng Kung University , No. 1, Ta‐Hsueh Road, Tainan 701, Taiwan |
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| Abstract: | Abstract This paper proposes a new switching architecture to be used in all optical packet switching networks. The proposed switch is derived from an original 2 × ?2 two‐stage multi‐buffer switched delay line based optical switching node, known as an M‐Quadro node. By incorporating bypass lines into the M‐Quadro architecture and employing a novel switch control strategy, the optical packet switching node can effectively resolve packet contentions, thus reducing the packet deflection probability substantially. Furthermore, we show that such architecture is scalable for a generic multiple stages optical packet switch with a larger number of input/output ports. |
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| Keywords: | switched delay line bypass line optical packet switching scalable |
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