Analysis and optimization of SDOI structure to maximize the intrinsic performance of extremely scaled MOSFETs |
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Authors: | Zhikuan Zhang Shengdong Zhang Chuguang Feng Mansun Chan |
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Affiliation: | Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China; |
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Abstract: | The advantages of using elevated S/D formed on oxide shallow trench isolation are studied in detail. By careful design, the short channel short channel effects can be suppressed by the elevated source/drain (S/D) structure. In addition, the S/D region parasitic capacitance is significantly suppressed by the silicon-on-insulator (SOI)-like S/D structure. Tradeoff between series resistance and gate-to-drain Miller capacitance can be achieved by carefully selecting the gate spacer thickness. With careful optimization of device geometry, both the gate-delay and power consumption can be significantly reduced together. Design guideline and potential performance gain with the S/D-on-insulator structure is discussed. |
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