Performance-Scalable Array Architectures for Modular Multiplication |
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Authors: | William L. Freking and Keshab K. Parhi |
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Affiliation: | (1) Department of Electrical and Computer Engineering, University of Minnesota, 200 Union St. SE, Minneapolis, MN 55455, USA |
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Abstract: | Modular multiplication is a fundamental operation in numerous public-key cryptosystems including the RSA method. Increasing popularity of internet e-commerce and other security applications translate into a demand for a scalable performance hardware design framework. Previous scalable hardware methodologies either were not systolic and thus involved performance-degrading, full-word-length broadcasts or were not scalable beyond linear array size. In this paper, these limitations are overcome with the introduction of three classes of scalable-performance modular multiplication architectures based on systolic arrays. Very high clock rates are feasible, since the cells composing the architectures are of bit-level complexity. Architectural methods based on both binary and high-radix modular multiplication are derived. All techniques are constructed to allow additional flexibility for the impact of interconnect delay within the design environment. |
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Keywords: | modular multipliers systolic computation pipelined architectures high-radix arithmetic implementation |
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