Highly reliable testing of ULSI memories with on-chip voltage-downconverters |
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| Authors: | Tsukude M. Arimoto K. Hidaka H. Konishi Y. Hayashikoshi M. Suma K. Fujishima K. |
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| Affiliation: | Mitsubishi Electr. Corp., Hyogo; |
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| Abstract: | Two testing techniques for ultra-large-scale integrated (ULSI) memories containing on-chip voltage downconverters (VDCs) are described. The first in an on-chip VDC tuning technique that adjusts internal VCC to compensate for the monitored characteristics of the process parameters during repair analysis testing. The second is an operating-voltage margin test, performed at various internal VCC levels during the water sort test (WT) and the final shipping test (FT) |
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