| 基于BSG的时延驱动布局 |
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| 引用本文： | 李翠超,严晓浪,李芝燕,马琪. 基于BSG的时延驱动布局[J]. 电路与系统学报, 2000, 5(1): 91-94 |
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| 作者姓名： | 李翠超 严晓浪 李芝燕 马琪 |
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| 作者单位： | 杭州电子工业学院微电子CAD研究所,杭州,310037 |
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| 摘 要： | 本文采用BSG (bounded slicing grid) 结构对时延驱动 (timing driven) 或称为性能驱动 (performance driven)布局问题进行了研究和实现，此算法是一种Non-slicing的面向路径的时延优化BBL (Building Block Layout)，算法思路简洁，易于实现，实验效果令人满意。
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| 关 键 词： | 时延驱动布局 BBL布局 集成电路 |
| 文章编号： | 1007-0249(2000)01-0091-04 |
| 修稿时间： | 1999-08-24 |
The BSG-Based Timing-driven Placement |
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| LI Cui-chao,YAN Xiao-lang,LI Zhi-yan,MA Qi. The BSG-Based Timing-driven Placement[J]. Journal of Circuits and Systems, 2000, 5(1): 91-94 |
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| Authors: | LI Cui-chao YAN Xiao-lang LI Zhi-yan MA Qi |
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| Abstract: | Timing-driven (or performance-driven) BBL placement based on BSG (bounded slicing grid) structure is studied and implemented. This is a Non-slicing path-oriented time-delay optimizing BBL algorithm .It is straightforward and easy to be implemented. Experiment result is satisfactory. |
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| Keywords: | BSG Timing-driven Non-slicing Path-oriented time-delay optimization BBL placement |
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