CMOS current‐steering DAC architectures based on the triple‐tail cell

In this paper two novel current‐steering digital‐to‐analog converter (DAC) architectures, exploiting the triple‐tail cell as switching element, are presented. The proposed solutions are theoretically analysed and design equations are carried out. The two architectures show better performance than the classical binary‐weighted solution and it is shown that they can profitably substitute the binary sub‐DAC section in a segmented topology. Theoretical results are compared with behavioural‐level simulations and confirm the effectiveness of the proposed architectures. Copyright © 2007 John Wiley & Sons, Ltd.