REFINE: The reconfigurable packet filtering on network processor

Network processors (NPs) are emerging as very promising platforms for developing reconfigurable and high‐performance network devices, due to their capability to combine the flexibility of general‐purpose processors with the high‐performance features of hardware‐based systems. They represent the most suitable solutions for implementing complex and dynamic tasks, such as packet classification and scheduling, which are key operations, for example, in DS networks. Programmability and reconfigurability allow NP‐based devices to be continuously adapted to the new network requirements, obtaining a high time in market. This paper illustrates the compound process that leads to the implementation of a reconfigurable multidimensional packet filtering on the Intel^® IXP2400 NP. The multidimensional multibit trie is chosen as the best algorithm to be implemented and it is modified to exploit the specific features of NP. The different tasks are mapped on the NP computational resources and an optimized implementation is performed, with subsequent experimental validation. Copyright © 2008 John Wiley & Sons, Ltd.