A self-calibration method for capacitance mismatch in SAR ADC with split-capacitor DAC |
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| Affiliation: | School of Electronic and Information Engineering, Tianjin University, Nankai, Tianjin 300072, China;Electronics Research Institute, Giza, Egypt;School of Microelectronics, Xidian University, No.2 South Taibai Road, Mailbox 373, Xi’an, Shaanxi 710071, China;Electrical Communication Engineering Department, Indian Institute of Science, Bangalore 560012, India;Department of Electrical Engineering, University of Zanjan, Zanjan, Iran;Electronics Research Institute, Giza, Egypt;State Key Laboratory of ASIC & System, Fudan University, Shanghai 201203, China |
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| Abstract: | A self-calibration method to calibrate the nonlinearity due to capacitance mismatch in successive approximation register (SAR) analog-to-digital converter (ADC) is presented. It focuses on calibrating the most significant bit (MSB) array in the split-capacitor main DAC (split-MDAC) by using a calibration DAC (CDAC) that contains multiple sub-CDACs. Every bit in MSB array has its corresponding sub-CDAC in CDAC, which enhances the calibration efficiency. To verify the calibration method, a 14 bit, 500 kS/s SAR ADC is implemented, and it is manufactured in 0.35 μm 2P4M CMOS process. The measured results show that the proposed calibration method can assist this SAR ADC to achieve better static and dynamic performance, and its ENOB is improved from 9 bit to 11.98 bit at Nyquist input frequency. |
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| Keywords: | Split-DAC Self-calibration Capacitance mismatch Calibration DAC array |
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