DC self-heating effects modelling in SOI and bulk FinFETs |
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| Affiliation: | 1. IUMA, Institute for Applied Microelectronics, Universidad de Las Palmas de Gran Canaria, Edificio de Electrónica y Telecomunicación, Campus Universitario de Tafira, 35017 Las Palmas, Spain;2. Departamento de Electrónica y Tecnología de los Computadores, Universidad de Granada, Facultad de Ciencias, Fuente Nueva s/n, 18071 Granada, Spain;3. Departament d׳Enginyeria Electrònica, Elèctrica i Automàtica, Universitat Rovira i Virgili, Escola Tècnica Superior d׳Enginyeria, Av. Dels Països Catalans, 26, 43007 Tarragona, Spain;4. Solid-State Electronics Section, CINVESTAV, Av. IPN 2508, 07360 Mexico D.F., Mexico;1. Department of Microelectronics, Faculty of Electrical Engineering and Communications, Brno University of Technology, Technicka 10, 616 00 Brno, Czech Republic;2. Department of Electrical Engineering, Faculty of Military Technologies, University of Defence, Kounicova 65, 662 10 Brno, Czech Republic;3. Department of Radio Electronics, Faculty of Electrical Engineering and Communications, Brno University of Technology, Technicka 10, 616 00 Brno, Czech Republic;1. Council for Scientific and Industrial Research, Meiring Naudé Road, Brummeria, Pretoria 0184, South Africa;2. Carl and Emily Fuchs Institute for Microelectronics, Dept. of Electrical, Electronic and Computer Engineering, University of Pretoria, Cnr Lynnwood and University Roads, Pretoria 0002, South Africa;3. Faculty of Engineering and the Built Environment, University of Johannesburg, Auckland Park Kingsway Campus, Auckland Park 2006, South Africa;1. Communications and Electronics Engineering Department, Mansoura University, Egypt;2. Electrical Engineering department, Al Imam Mohammad Ibn Saud Islamic University (IMSIU), Riyadh, Saudi Arabia |
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| Abstract: | DC thermal effects modelling for nanometric silicon-on-insulator (SOI) and bulk fin-shaped field-effect transistors (FinFETs) is presented. Among other features, the model incorporates self-heating effects (SHEs), velocity saturation and short-channel effects. SHEs are analysed in depth by means of thermal resistances, which are determined through an equivalent thermal circuit, accounting for the degraded thermal conductivity of the ultrathin films within the device. Once the thermal resistance for single-fin devices has been validated for different gate lengths and biases, comparing the modelled output characteristics and device temperatures with numerical simulations obtained using Sentaurus Device, the thermal model is extended by circuital analysis to multi-fin devices with multiple fingers. |
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| Keywords: | Fin-shaped field-effect transistor (FinFET) Self-heating effects (SSE) Thermal resistance Compact modelling |
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