Improved performance of nanoscale junctionless transistor based on gate engineering approach |
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| Affiliation: | 1. Department of Electronics and Applied Physics, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, 4259-S2-20 Nagatsuta-cho, Midori-ku, Yokohama, Kanagawa 226-8502, Japan;2. Toshiba Material Co., LTD, 8, Shinsugita-Cho, Isogo-Ku, Yokohama 235-8522, Japan;3. Frontier Research Center, Tokyo Institute of Technology, 4259-S2-20 Nagatsuta-cho, Midori-ku, Yokohama, Kanagawa 226-8502, Japan;1. Department of Physics, College of Science, University of Bahrain, P.O. Box 32038, Bahrain;2. Department of Basic Medical Sciences, Royal College of Surgeons in Ireland, Medical University of Bahrain, P.O. Box 15503, Bahrain |
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| Abstract: | In this paper, we propose an effective method to improve the electrical characteristics of dual-material-gate (DMG) junctionless transistor (JLT) based on gate engineering approach, with the example of n-type double gate (DG) JLT with total channel length down to 30 nm. The characteristics are demonstrated and compared with conventional DMG DGJLT and single-material gate (SMG) DGJLT. The results show that the novel DMG DGJLT presents superior subthreshold swing (SS), drain-induced barrier lowering (DIBL), transconductance (Gm), ON/OFF current ratio, and intrinsic delay (τ). Moreover, these unique features can be controlled by engineering the length and workfunction of the gate material. In addition, the sensitivities of the novel DMG device with respect to structural parameters are investigated. |
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| Keywords: | Dual-material gate (DMG) Double gate (DG) Junctionless transistor (JLT) DIBL ON/OFF current ratio |
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