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Memristor based N-bits redundant binary adder |
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| Affiliation: | 1. NISC Research Center, Nile University, Cairo, Egypt;2. Engineering Mathematics and Physics Dept., Faculty of Engineering, Cairo University, Cairo, Egypt;1. Department of Urology, Jikei University School of Medicine, Tokyo, Japan;2. Department of Pathology, Jikei University School of Medicine, Tokyo, Japan;1. School of Physics, Huazhong University of Science and Technology, Wuhan 430074, China;2. School of Physics, Nankai University, Tianjin 300071, China;3. State Key Laboratory of ITP, ITP-CAS, Beijing 100190, China;1. Digital Design Group SK Hynix Memory Solutions, San Jose, California 95133, USA;2. Department of Electrical and Computer Engineering, Stony Brook University, Stony Brook, New York 11794, USA |
| Abstract: | This paper introduces a memristor based N-bits redundant binary adder architecture for canonic signed digit code CSDC as a step towards memristor based multilevel ALU. New possible solutions for multi-level logic designs can be established by utilizing the memristor dynamics as a basis in the circuit realization. The proposed memristor-based redundant binary adder circuit tries to achieve the theoretical advantages of the redundant binary system, and to eliminate the carry (borrow) propagation using signed digit representation. The advantage of carry elimination in the addition process is that it makes the speed independent of the operands length which speeds up all arithmetic operations. One memristor is sufficient for both the addition process and for storing the final result as a memory cell. The adder operation has been validated via different cases for 1-bit and 3-bits addition using HP memristor model and PSPICE simulation results. |
| Keywords: | Memristor Adder Redundant binary Multi-level digital circuits Ternary Carry free adders |
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