Short-channel effect and device design of extremely scaled tunnel field-effect transistors

For serving as ideal switching devices in future energy-efficient applications, scaling down the channel lengths of tunnel-field effect transistors (TFETs) is essential to follow the pace of Si-based CMOS technologies. This work elucidates the short-channel mechanisms and the role of the drain in extremely-scaled TFETs. The scalability of TFETs depends strongly on the appropriately low drain concentration, whereas the capability of the drain for scaling relies on a sufficient drain region. The drain with a light concentration of 5 × 10¹⁷ cm⁻³ and a minimum length of 20 nm enables 5 nm TFETs to exhibit favorable on–off switching characteristics. In sub-20 nm TFETs, the total drain and channel lengths must satisfy the minimum criteria of approximately 25 nm to sustain reversely biased drain voltage of 0.7 V. The asymmetric Si_1−xGe_x source heterojunction is combined with the minimum drain design in 5 nm TFETs to separately optimize the source- and drain-side tunnel junctions, generating ideal on-/off-currents and switching characteristics to serve as a promising design approach of sub-5 nm TFETs.