Thermal resistance of side by side multi-chip package: Thermal mode analysis |
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| Affiliation: | 1. School of Mechanical Engineering, Southeast University, Nanjing, 211189, People’s Republic of China;2. College of Electronic and Optical Engineering & College of Microelectronics, Nanjing University of Posts and Telecommunications, Nanjing, 210003, People’s Republic of China;3. National and local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology, Nanjing University of Posts and Telecommunications, Nanjing, 210003, People’s Republic of China |
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| Abstract: | The thermal mode analysis is used in this paper to optimize the thermal management with optimal locations and chip sizes for multi-chip package. The average thermal resistance is defined and analyzed. The spreading thermal resistance can be expanded into Fourier series so that the thermal modes can be established. For the infinite thermal modes, only a few terms are needed to be considered due to the rapid convergence of solution. The optimal locations and chip sizes can then be determined by using the first few modes to reduce the thermal resistance as minimal as possible. The optimal locations have the cosine wave property so that the wave nodes might be the suitable sites. On the other hand, the optimal chip sizes have the cardinal sine property which decays monotonously. For given optimal locations, the optimal chip sizes are determined by certain modes. These special modes can be used to analyze the range of optimal locations and chip sizes. |
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| Keywords: | Multi-chip package Fourier series expansion Thermal resistance matrix Thermal mode analysis |
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