CSAM: A clock skew-aware aging mitigation technique |
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Affiliation: | 1. School of Electrical and Computer Engineering, University of Tehran, Iran;2. Department of Electrical Engineering, Shahed University, Iran;3. Department of EE-Systems, University of Southern California, United States;1. Department of Statistics, Alpen-Adria-Universität Klagenfurt, Klagenfurt, Austria;2. Infineon Technologies Austria AG, Villach, Austria;1. School of Chemistry and Environment, South China Normal University, Guangzhou 510006, PR China;2. National Testing Center for Optical Radiation Safety of Photoelectric Products, Huizhou 516003, PR China;3. EVE Energy Co. Ltd, Huizhou 516006, PR China;1. Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, Cerdanyola del Valles, Spain;2. Departamento de Materia Condensada, GIA, GAIANN, CAC, Comisión Nacional de Energía Atómica, Buenos Aires, Argentina;1. School of Reliability and Systems Engineering, Beihang University, Beijing 100191, China;2. Avic Aviation Motor Control System Institute, Wuxi 214000, China;3. Center for Advanced Life Cycle Engineering (CALCE), University of Maryland, USA |
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Abstract: | In this work, we propose a clock skew-aware aging mitigation (CSAM) technique which considers the effect of asymmetric aging both on logic path and clock tree together. Simultaneous consideration of both parts in the design optimization problem enables us to reduce the area overhead while increasing the lifetime. For the aging mitigation of the logic path, we make use of both internal node control (INC) and input vector control (IVC) techniques while, for the clock tree circuits, a proper choice between NAND or NOR based integrated clock gating (ICG) cell is made. The optimization may be performed based on two objective functions of maximizing lifetime or minimizing the area overhead for a predetermined clock frequency and lifetime. To assess the efficacy of the proposed technique, we compared the lifetimes and area overheads for a set of circuits from ISCAS89 and ITC99 benchmark suites when CSAM and conventional techniques are used. The results, obtained using SPICE simulations for the circuits in a 45-nm technology, reveals that an average lifetime improvement of 34% and an average area overhead reduction of 25.7% for the two objective functions, respectively. |
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Keywords: | Aging NBTI Clock skew Lifetime Optimization |
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