Two-level switching pattern deadbeat DSP controlled PWM inverter

A two-level switching algorithm of the deadbeat controlled PWM inverter is presented. Two levels, instead of three levels, are used in the pulse pattern. This scheme allows the use of higher switching frequency for a given computation time delay, which results in lower total harmonic distortion (THD) at the output. Control algorithms are derived. The proposed control scheme is implemented using a TI TMS320C14 DSP controlling an inverter to produce a very low THD sinusoidal output voltage. Simulation and experimental results are presented to verify the performance