多位平面并行的EZW零树编码电路研究

零树编码技术已经被MPEG-4国际标准所采用，多位平面并行的EZW零树编码电路方案为实时应用中的零树编码提供了一条高效的技术途径，它具体包括一种简单、巧妙的预处理器，对不同位平面之间存在的关联加以分离，保证多位平面并行零树编码的实现。另外，在每个位平面中，此方案利用符号分配与跳过处理的执行特点，将编码操作分解成两步，分别结合到两次正、反向的树深度扫描之中，避免了不规则的扫描、处理。此设计在FPGA电路上进行了验证，它可以实时编码CIF格式视频图像，需要2500个左右的逻辑单元。

EZW Zerotree Encoder Architecture Based on Parallel Processing of Multi-Bit-Planes

Zerotree coding technique has been adopted by MPEG 4 for static texture coding An EZW encoder architecture is proposed based on parallel processing of multi bit planes; it can be used for real time applications Under the architecture, an effective preprocessor is designed to make each bit plane independent for parallel processing on multi bit planes In addition, zerotree coding on each bit plane are divided into two stages based on the symbol definition and skip processing The two stages are arranged in two tree depth scans to avoid disorderly scan and processing The architecture is tested on a system with an FPGA chip and it uses about 2500 logic cells It is capable of encoding CIF images for real time applications