| 数据通信中交织与解交织的FPGA实现 |
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| 引用本文： | 范寒柏,宋文妙. 数据通信中交织与解交织的FPGA实现[J]. 华北电力大学学报(自然科学版), 2002, 29(2): 84-87 |
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| 作者姓名： | 范寒柏 宋文妙 |
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| 作者单位： | 华北电力大学电子与通信工程系,河北保定,071003 |
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| 摘 要： | 介绍了数据通信中抗突发连串错码而采用交织和解交织技术。对利用ＦＰＧＡ实现交织器和解交织器中读写地址的产生方法进行了比较和深入的探讨。结合ＦＰＧＡ（现场可编程门阵列）器件的特点，基于ＥＤＡ技术，实现了按位的交织和解交织器。该交织器和交织器模块已成功地应用于某专用数字系统。
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| 关 键 词： | 交织器 解交织器 LPM 地址序列 FPGA |
| 文章编号： | 1007-2691(2002)02-0084-04 |
| 修稿时间： | 2001-06-15 |
Realizations of interleaving and deinterleaving in digital communication based on FPGA |
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| FAN Han-bai,SONG Wen-miao. Realizations of interleaving and deinterleaving in digital communication based on FPGA[J]. Journal of North China Electric Power University, 2002, 29(2): 84-87 |
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| Authors: | FAN Han-bai SONG Wen-miao |
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| Abstract: | The interleaving and deinterleaving in data communication has been introduced to deal with the burst-error in relay channel. Several address generation techniques utilizing FPGA has been compared and discussed in detail. Combining the FPGA device of ALTERA company, the in-bit interleaver and deinterleaver based on EDA technology have been developed and used in a digital system successfully. |
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| Keywords: | interleaving deinterleaving LPM address sequence FPGA |
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