A Method for Reducing the Dead‐Time Voltage and Impedance Voltage in a Series Voltage Compensator |
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| Authors: | Atsushi Nakata Masahiro Nozaki Akihiro Torii Akiteru Ueda |
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| Affiliation: | 1. Aichi Institute of Technology, Japan;2. Momozono Densetsu, Ltd., Japan |
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| Abstract: | Many research groups are developing series voltage compensators. In a series converter, since a transformer is used in series in the power system, the power system current flows into the voltage source inverter through the transformer. The inverter current, which is determined by the transformation ratio, gives rise to an error voltage that consists of a dead‐time voltage and an impedance voltage. The error voltage is generated even when the reference voltage is zero. This paper describes the mechanism by which the error voltage occurs and proposes a method for reducing the error voltage. © 2013 Wiley Periodicals, Inc. Electr Eng Jpn, 186(3): 85–93, 2014; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.22333 |
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| Keywords: | series voltage compensator dead‐time voltage impedance voltage |
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