Affiliation: | aDept. Materials Science and Engineering, Chosun University, Kwangju 501-759, South Korea bDept. Metallurgical Engineering, Kookmin University, Seoul 136-702, South Korea |
Abstract: | The deformation in the hysteresis loop of Pt/Pb(Zr,Ti)O3/Pt capacitors has been investigated by varying the annealing temperature after patterning the top sputter-deposited electrode using reactive ion etching (RIE) with Ar gas. It was observed that as-patterned capacitors were positively poled by the dc plasma potential during RIE of Pt. Voltage shift and slant in the hysteresis loop are found to be due to space charges trapped at domain boundaries during both sputtering and RIE rather than a nonferroelectric second phase. As Zr:Ti ratio decreases, internal bias field increases, and annealing temperature, at which maximum in polarization occurs, also increases due to lower permittivity and higher Curie temperature. |