Memory characteristics of a self-assembled monolayer of Pt nanoparticles as a charge trapping layer |
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Authors: | Choi Hyejung Choi Byung-Sang Kim Tae-Wook Jung Seung-Jae Chang Man Lee Takhee Hwang Hyunsang |
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Affiliation: | Department of Materials Science and Engineering, Gwangju Institute of Science and Technology, #261, Cheomdan-gwagiro, Buk-gu, Gwangju 500-712, Korea. |
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Abstract: | A self-assembled monolayer of Pt nanoparticles (NPs) was studied as a charge trapping layer for non-volatile memory (NVM) applications. Pt NPs with a narrow size distribution (diameter ~4?nm) were synthesized via an alcohol reduction method. The monolayer of these Pt NPs was immobilized on a SiO(2) substrate using poly(4-vinylpyridine) (P4VP) as a surface modifier. A metal-oxide-semiconductor (MOS) type memory device with Pt NPs exhibits a relatively large memory window of 5.8?V under ± 7?V for program/erase voltage. These results indicate that the self-assembled Pt NPs can be utilized for NVM devices. |
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