改进部分积压缩结构的快速乘法器

针对16位乘法器运算速度慢、硬件逻辑资源消耗大的问题，采用华莱士树压缩结构，通过对二阶布思算法、4-2压缩器和保留进位加法器的优化组合使用及对符号数采用合理的添、补、删策略，实现16位符号数快速乘法器的优化设计。该乘法器采用SMIC 0.18 μm工艺标准数字单元库，使用Synopsys Design Compiler综合实现，在1.8 V, 25℃条件下，芯片最大路径延时为3.16 ns，内核面积为 50 452.75 μm2，功耗为5.17 mW。

High-speed Multiplier of Optimizing Partial Products Constrictive Structure

To solve the problem of low speed and large logic resource consuming in 16-bit high speed multipler design,Wallace tree structure combined with several methods such as Booth algorithm,4-2 compressor with Carry Save Adder（CSA）,and reasonable adding,padding and deleting of the signed number are used to optimize the whole design.Under 1.8 V supply and 25℃ condition,the multiplier is synthesized in SMIC 0.18 μm technology with Synopsys Design Compiler with a 3.16 ns maximal path delay and a core chip area of 50 452.75 μm2.The power dissipation is 5.17 mW.