Influence of process steps on the performance of microcrystalline silicon thin film transistors |
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Authors: | Maher Oudwan Alexey Abramov Pere Roca i Cabarrocas |
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Affiliation: | a CEA-LETI, 17, rue des Martyrs, 38054 Grenoble cedex, France b Laboratoire de Physique et des Interfaces des Couches Minces (UMR 7647) LPICM Ecole Polytechnique F-91128 Palaiseau Cedex, France |
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Abstract: | Bottom gate microcrystalline silicon thin film transistors (μc-Si TFT) have been realized with two types of films: μc-Si(1) and μc-Si(2) with crystalline fraction of 80% and close to 100% respectively. On these TFTs we applied two types of passivation (SiNx and resist). μc-Si TFTs with resist as a passivation layer present a low leakage current of about 2.10− 12 A for VG = − 10 and VD = 0.1V an ON to OFF current ratio of 106, a threshold voltage of 7 V, a linear mobility of 0.1 cm2/V s, and a sub-threshold voltage of 0.9 V/dec. Microcrystalline silicon TFTs with SiNx as a passivation present a new phenomenon: a parasitic current for negative gate voltage (− 15 V) causes a bump and changes the shape of the sub-threshold region. This excess current can be explained by and oxygen contamination at the back interface. |
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Keywords: | TFT Microcrystalline silicon Active matrix |
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