Process and reliability of air-gap Cu interconnect using 90-nm node technology |
| |
Authors: | Noguchi J Sato K Konishi N Uno S Oshima T Ishikawa K Ashihara H Saito T Kubo M Tamaru T Yamada Y Aoki H Fujiwara T |
| |
Affiliation: | Micro Device Div., Hitachi Ltd., Tokyo, Japan; |
| |
Abstract: | A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for gap formation; and 4) the preservation of mechanical integrity. In this paper, the air-gap Cu metallization was applied to 130- and 90-nm node CMOS. Four levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the technology was investigated. There were distinct improvements of the leakage current and the time-dependent dielectric breakdown characteristic by the application of an air-gap. Moreover, the air-gap interconnect was further improved with a selective W sealing process. This results in a drastic reduction of the capacitance and the effective dielectric constant. |
| |
Keywords: | |
|
|