Genetic framework for the high level optimisation of low power VLSIDSP systems

The authors present a technique for optimising CMOS based DSP systems for power. A genetic algorithm is used to reduce power, while tracking area and speed specifications, through the application of high level transformations. The algorithm searches for systems with the lowest power consumption within a large solution space. Results are presented which demonstrate the efficiency of the genetic algorithm as a power optimisation tool for complex VLSI systems