n-Channel Si-gate process for MNOS EEPROM transistors

An n-channel Si-gate process has been developed to fabricate MNOS EEPROM transistors and fast logic circuits on one chip. The technology proposed involves low thermal oxidation temperatures ≤900°C after nitride deposition, two LOCOS process steps and application of self-aligned overlapped poly-Si contacts. The MNOS memory transistors obtained have been programmed by ±25 V pulses with a write time of t_w = 10 ms and an erase time of t_e = 100 ms.The retention data have been found to be dependent on nitride thickness and threshold voltage shift, but independent of channel length and channel doping. For devices with a nitride thickness of 30.5 nm the short-term decay rate of 0.6 V/(decade of time) has been determined. Endurance testing using up to 10⁷ pulses of ±25 V, 100 μs corresponding to approx. 10⁴ write/erase cycles showed no time dependence for the decay rate over the time of 10⁵ min in which retention measurements were made.