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Soft computing‐based approach for optimal design of on‐chip comparator and folded‐cascode op‐amp using colliding bodies optimization
Authors:Bishnu Prasad De  R. Kar  D. Mandal  S. P. Ghoshal
Abstract:This paper presents an efficient approach for the optimal designs of two analog circuits, namely complementary metal oxide semiconductor) two‐stage comparator with p‐channel metal oxide semiconductor input driver and n‐channel input and folded‐cascode operational amplifier using a recently proposed meta‐heuristic‐based optimization algorithm named as colliding bodies optimization (CBO). It is a multi‐agent algorithm that does not depend upon any internal control parameter, making the algorithm extremely simple. The main objective of this paper is to optimize the metal oxide semiconductor (MOS) transistors' sizes using CBO in order to reduce the areas occupied by the circuits and to get better performance parameters of the circuits. Simulation Program with Integrated Circuit Emphasis simulation has been carried out by using the optimal values of MOS transistors' sizes and other design parameters to validate that CBO‐based design is satisfying the desired specifications. Simulation results demonstrate that the design specifications are closely met and the required functionalities are achieved. The simulation results also confirm that the CBO‐based approach is superior to the other algorithms in terms of MOS area and performance parameters like gain, power dissipation, etc., for the examples considered. Copyright © 2016 John Wiley & Sons, Ltd.
Keywords:evolutionary optimization techniques  CMOS  circuit sizing  folded‐cascode op‐amp  CMOS comparator  CBO
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