Defect requirements for advanced 300 mm DRAM substrates

In the background of increasing requirements for advanced 300 mm DRAM substrates, the possibilities of balancing defect requirements versus cost and feasibility are discussed. For DRAMs based on deep trench capacitors, the main focus regarding defects is on voids, so-called crystal originated pits (COPs), which are present in the commonly used vacancy rich silicon crystals. Whereas for the material used for recent DRAM design rules, the typical COP sizes around 150 nm have still been sufficiently small not to deteriorate the yield of the DRAM products, for future design rules a reduction of COPs in the device active area will be required. Since the conversion to 300 mm wafers is purely cost driven, a solution has to be found for making 300 mm low defect wafers cost effective for the usage even on products under a high cost pressure like DRAM.A promising material option is 300 mm high temperature annealed wafers, which are on the one hand able to fulfil the future requirements in terms of performance and offer on the other hand also the potential to become a cost effective substrate by implementation of cost saving opportunities. The task of the wafer users is to critically review the requirements and to identify essential needs in contrast to “nice to have” items. For 300 mm annealed wafers, the requirements regarding COP reduction and slip performance are discussed.