An empirical I‐V model of tunneling real‐space transfer transistors for monostable–bistable transition logic element application

We proposed an empirical I‐V model to represent the negative differential resistance (NDR) regime of fabricated tunneling real‐space transfer transistors (TRSTTs). For TRSTTs to have great potential in monostable–bistable transition logic element (MOBILE) design, our model is able to accurately reproduce the NDR regime including gate‐source‐bias‐controlled NDR values and modulated peak to valley drain current ratios. The modeled I‐V curves, tranconductances, and NDRs with multiple gate biases are in good agreement with measured data. The key parameters in the model have clear physical meanings, and the value of these parameters is easy to be extracted directly from the test I‐V curves. The model is used to simulate a practical MOBILE, and excellent agreement between the simulated and measured data was found. Copyright © 2015 John Wiley & Sons, Ltd.