DDFSGEN |
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Authors: | Linda Kwai-Lin Lau Rajeev Jain Henry Samueli Henry T Nicholas III and Etan G Cohen |
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Affiliation: | (1) Electrical Engineering Department, UCLA, 90024 Los Angeles, CA |
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Abstract: | This paper presents a functional compiler for the automatic design of Direct Digital Frequency Synthesizer (DDFS) integrated circuits (ICs) using a ROM based table look-up architecture. The compiler allows the user to specify high-level specifications such as the acceptable spurious response and it generates the IC architecture, floorplan, and layout. To construct the layout for different specifications, a library of parameterized macrocells has been developed in 1.2 m CMOS technology.A test chip with a quadrature DDFS module has been generated, using the compiler, and fabricated. The chip has two input signals: one is for frequency control while the other is for phase initialization. Input and output word lengths are 16 bits and 6 bits respectively. The chip complexity is approximately 12,000 transistors (DDFS core) and the die size is 4.8×2.9mm
2. A maximum sample rate of 80 MHz has been attained implying a maximum sine (cosine) output frequency of 40 MHz and a frequency resolution of 1.22 kHz. The maximum spurious level measured is –46 dB. |
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