Evaluation of the Interface Accuracy for Power Hardware-in-the-Loop Experiments

Selecting an accurate interface algorithm is a primary goal in order to have a successful operation of power hardware-in-the-loop. The purpose of this paper is to utilize the modified damping impedance method for testing the accuracy of the interface algorithm in power hardware-in-the-loop applications in comparison to the traditional damping impedance method and ideal transformer model interfaces. The hardware-in-the-loop test-bed (a power-electronic-based system) is utilized to experimentally analyze and validate the expected advantages of the modified damping impedance method. In addition, to evaluate the power hardware-in-the-loop accuracy, a transfer function perturbation-based approach is considered to validate the results of experimentation analytically and quantitatively.