| 应用于雷达系统的双路高速数据采集存储系统设计 |
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| 引用本文： | 刘文茹,张云华.应用于雷达系统的双路高速数据采集存储系统设计[J].测试技术学报,2012,26(5):446-451. |
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| 作者姓名： | 刘文茹 张云华 |
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| 作者单位： | 1. 中国科学院微波遥感技术重点实验室,北京100190;中国科学院研究生院,北京100049
2. 中国科学院微波遥感技术重点实验室,北京,100190 |
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| 摘 要： | 介绍了一种用于对雷达回波I/Q信号进行双路高速采集与数据存储的系统,采样速率为200MHz,分辨率为12位,存储深度为4GB.该系统采用FPGA作为主控制器,ADS62P29作为高速数据转换器,K9K8G08U0M作为大容量数据存储器,通过USB实现系统与计算机之间的通信.利用Cadence软件和VHDL语言完成了系统设计、软件仿真及关键信号的完整性仿真.测试结果表明,ADC的有效位数可达10.69,输入信号为80 MHz的正弦信号时,两路ADC信号之间的相干系数达到0.998 4,可满足雷达系统对回波信号进行高精度相位测量的要求.
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| 关 键 词： | 雷达 FPGA 高速AD 大容量存储器 信号完整性 |
High Speed Data Acquisition Storage System Design for Radar |
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| LIU Wenru
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ZHANG Yunhua.High Speed Data Acquisition Storage System Design for Radar[J].Journal of Test and Measurement Techol,2012,26(5):446-451. |
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| Authors: | LIU Wenru ZHANG Yunhua |
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| Affiliation: | 1(1.The Key Laboratory of Microwave Remote Sensing,Chinese Academy of Sciences,Beijing 100190,China;2.Graduate University of the Chinese Academy of Sciences,Beijing 100049,China) |
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| Abstract: | The paper introduces a high-speed data acquisition storage system with two channels applied to sampling the echo signals of radar receiver.The developed system can work at a sampling rate of 200 MHz with a 12-bit resolution and the 4 G bytes storage.The FPGA acts as the control core of the system,the ADS62P29 is used as the high-speed data converter,and the K9K8G08U0M is used as the large capacity data storage.The communication between the system and the computer is through USB.The cadence and VHDL are used to complete the system design,software simulation and signal integrity simulation.Test results show that the ADC ENOB is 10.69 and the synchronization between two channels are satisfied. |
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| Keywords: | radar FPGA high-speed AD large capacity memory signal integrity |
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