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16-Mb synchronous DRAM with 125-Mbyte/s data rate |
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| Authors: | Yunho Choi Myungho Kim Hyunsoon Jang Taejin Kim Seung-hoon Lee Ho-cheol Lee Churoo Park Siyeol Lee Cheol-soo Kim Sooin Cho Ejaz Haq Karp J. Daeje Chin |
| Affiliation: | Samsung Electronics, Kyungki-Do; |
| Abstract: | In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M×8) achieves a 125-Mbyte/s data rate using 0.5-μm twin well CMOS technology |
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