Closed-Loop Nonlinear Modeling of Wideband$SigmaDelta$Fractional-$N$Frequency Synthesizers

Wideband low-noise$SigmaDelta$fractional-$N$synthesizers pose several design challenges due to the nonlinear time-varying nature of synthesizer building blocks such as phase frequency detectors (PFDs), charge pump, and frequency dividers. Loop nonlinearities can increase close-in phase noise and enhance spurious tones due to intermodulation of high-frequency quantization noise and tonal content; therefore, an accurate simulation model is critical for successful implementation of loop parameters and bandwidth widening techniques. In this paper a closed-loop nonlinear simulation model for fractional-$N$synthesizers is presented. Inherent nonuniform sampling of the PFD is modeled through an event-driven dual-iteration-based technique. The proposed technique generates a vector of piecewise linear time–voltage pairs, defining the voltage-controlled oscillator (VCO) control voltage. This method also lends itself to modeling of cyclostationary thermal and flicker noise generated by time-varying charge-pump current pulses. A flexible third-order$SigmaDelta$modulated RF synthesizer core with integrated loop filter and LC-tank VCO is designed and fabricated in 0.13-$muhbox m$CMOS process in order to validate the technique experimentally. The proposed modeling technique was able to predict in-band spur power levels with 1.8-dB accuracy, and spur frequency offsets with lower than 400-Hz accuracy with several programmable nonidealities enabled.