Controlling the ON-resistance in SOI LDMOS using parasitic bipolar junction transistor |
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Authors: | Avikal Bansal M Jagadesh Kumar |
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Affiliation: | 1. Department of Electrical Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi?, 110 016, India
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Abstract: | We present a new parasitic bipolar junction transistor (BJT) enhanced silicon on insulator (SOI) laterally double diffused metal oxide semiconductor (LDMOS), called BJT enhanced LDMOS (BE-LDMOS). The proposed device utilizes the parasitic BJT present in an LDMOS to increase the drain current for a given gate voltage, resulting in a reduction in the ON-resistance by 26.2 % and improving the switching speed by 7.8 % for BE-LDMOS as compared to the comparable LDMOS. These improvements are without degradation in other performance parameters such as off state breakdown voltage and transconductance. The process steps for fabricating BE-LDMOS are same as that for LDMOS except for an additional metal contact. |
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