Novel PLL-based clock distribution scheme |
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Authors: | Embabi SHK Islam KI |
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Affiliation: | Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA; |
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Abstract: | A technique for minimising clock skew in VLSI chips and multichip modules is proposed. A phase-locked loop is used to tune the delay of the clock interconnects. Negative, zero and positive delays can be achieved. This allows for clock synchronisation between individual modules with locally optimised clock distribution to minimise global clock-skew.<> |
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