| 高性能IPv6转发引擎的FPGA实现 |
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| 引用本文： | 乔世杰,韩毅,冯涛,彭海清,吴捷. 高性能IPv6转发引擎的FPGA实现[J]. 计算机工程与应用, 2006, 42(16): 121-123,152 |
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| 作者姓名： | 乔世杰 韩毅 冯涛 彭海清 吴捷 |
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| 作者单位： | 中兴通讯新技术研究部,深圳,518057;深圳中兴集成电路有限公司,深圳,518058 |
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| 基金项目： | 国家高技术研究发展计划(863计划) |
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| 摘 要： | 高速转发引擎是高性能IPv6路由器的关键技术,文章设计了一种IPv6高速转发引擎的硬件结构,编写了硬件结构的VerilogHDL模型,进行了仿真和逻辑综合,并成功用XILINX的FGPA对转发引擎进行了验证。测试结果表明,该文设计的转发引擎的结构正确,可以达到2.5G端口线速转发,满足了设计要求。
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| 关 键 词： | IPv6 转发引擎 FPGA Verilog HDL |
| 文章编号： | 1002-8331-（2006）16-0121-03 |
| 收稿时间： | 2006-02-01 |
| 修稿时间： | 2006-02-01 |
FPGA Implementation of a High Performance IPv6 Forwarding Engines |
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| Qiao Shijie,Han Yi,Peng Haiqing,Wu Jie,Feng Tao. FPGA Implementation of a High Performance IPv6 Forwarding Engines[J]. Computer Engineering and Applications, 2006, 42(16): 121-123,152 |
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| Authors: | Qiao Shijie Han Yi Peng Haiqing Wu Jie Feng Tao |
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| Affiliation: | 1Dept. of Advanced Technology,ZTE Corporation,Shenzhen 518057; 2Shenzhen ZTEIC Design Co.,LTD, Shenzhen 518058 |
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| Abstract: | It is a key technique for design high speed forwarding engines for IPv6 routers.This paper first proposes an efficient hardware architecture for high speed IPv6 forwarding engines.The verilog HDL code for the architecture are coded,simulated and synthesized.Then the forwarding engines are verified by xilix FPGA and the results show that the architecture is correct and the packet can be forwarded in 2.5G line rate. |
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| Keywords: | IPv6 FPGA Verilog HDL |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
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