An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch |
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| Authors: | Nikoozadeh A. Murmann B. |
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| Affiliation: | Dept. of Electr. Eng., Stanford Univ., CA; |
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| Abstract: | This brief analyzes the effect of load capacitor mismatch on the offset of a regenerative latch comparator. Two analytical models are presented and compared with HSpice simulations. Our results indicate that in a typical 0.18-mum CMOS latch, a capacitive imbalance of only 1 fF can lead to offsets of several tens of millivolts |
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